The present invention relates to semiconductor integrated circuit devices, and in particular to a dynamic random access memory device having a programmable refresh period and/or a programmable bit organization.
Dynamic random access memory circuits (DRAMs) are xe2x80x9cdynamicxe2x80x9d in that the stored data, typically represented by charged and discharged capacitors or memory cells, dissipate after a relatively short period of time. Thus, to retain the information, the stored data in the DRAM must be refreshed; that is, each capacitor must be periodically charged or discharged to maintain the capacitor""s charged or discharged state. The maximum time allowable between refresh operations depends on the charge storage capabilities of the capacitors that make up the memory cells in the array. The memory device manufacturer typically specifies a refresh time that guarantees data retention in the memory cells.
FIG. 1 is a block diagram of a conventional dynamic random access memory device 1. In FIG. 1, an array 10 includes a plurality of memory cells (not shown), which are typically arranged in rows and columns such that a particular memory cell may be addressed by specifying the memory cell""s row and column within the array. A signal on a word line, which a row decoder 20 selects according to an address from a row address buffer 16, turns on pass transistors in a selected row of memory cells to connect the memory cells to sense amplifiers 30 that detect the data in the memory cells. In a read operation, a data output multiplexer 32 chooses some of the data signals from the sense amplifiers 30 according to a predetermined bit organization of the memory device, and then the data thus chosen is output via a data output buffer 34. A bit organization select circuit 80 is an option circuit that determines the bit organization of the memory device.
A refresh operation is similar to a read operation but does not output data. The sensing of the data in the cells by the sense amplifiers 30 simultaneously rewrites the data to the cells. The data in the selected row of memory cells is thus xe2x80x9crefreshedxe2x80x9d. A row address for the refresh operation is from a refresh counter 18. A refresh period select circuit 50 is an option circuit that determines an interval or period between refresh operations, and the refresh counter 18 internally generates a row address according to the refresh period determined by the refresh period select circuit 50.
FIG. 2 is a circuit diagram of the refresh period select circuit 50. The refresh period select circuit 50 includes a PMOS transistor 52, a fuse 54 (e.g., a laser fuse or an electric fuse), NMOS transistors 56, 58, and 60, and inverters 62, 64, 66, and 68 connected as illustrated in FIG. 2. The refresh period select circuit 50 outputs a select signal RFS for determining a refresh period of the memory device, for example, a 1 K-refresh period, a 2 K-refresh period, or a 4 K-refresh period. A logic level of the select signal RFS depends on whether the fuse 54 is intact or open. This configuration does not permit a change of the refresh period after the fuse 54 is cut or blown.
FIG. 3 is a circuit diagram of the bit organization select circuit 80. The bit organization select circuit 80 is coupled to an option pad, and includes NMOS transistors 82 and 90, PMOS transistors 84, 86, and 88, a resistor RI, and inverters 92, 94, and 96 connected as illustrated in FIG. 3. The bit organization select circuit 80 outputs a select signal IOS for determining a bit organization of the memory device, for example, xc3x971, xc3x974, xc3x978, or xc3x9716. A logic level of the select signal IOS is according to a potential of the option pad, which a metal option connects to either a power supply voltage or a ground voltage. This configuration does not permit a change in the bit organization of the memory device because a metal option selects the bit organization.
As a result, since an option circuit that uses a fuse or a pad and a metal option determines the refresh period and the bit organization, the conventional memory device cannot change the refresh period or the bit organization when necessary.
In accordance with an aspect of the invention, a dynamic random access memory can program and change a bit organization and a refresh period.
One embodiment of the invention is a memory device that includes: an array of memory cells arranged in rows and columns; a row selector that selects one of the rows in response to a row address; a first generator of a plurality of refresh period select signals; and a second generator of the row address according to a refresh period during a refresh operation. The first generator responds to a mode set command and an address to determine which of the refresh period select signals are activated. The refresh period is determined by an activated one of the refresh period select signals.
In this embodiment, the means for generating a plurality of refresh period select signals typically includes a mode register set. The mode register set can be programmed according to the address supplied at an input of the mode set command, and the mode register set circuit outputs decoded signals for a refresh period set. The means for generating a plurality of refresh period select signals can further include a signal generator. The signal generator receives the decoded signals and outputs the refresh period select signals in response thereto, wherein a value stored in the mode register set determines which one of the refresh period select signals is activated.